display wiring #1

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rasmus · 2026-09-13T23:34:16+02:00

rasmus commented

2026-09-13 23:34:16 +02:00

The Underlying Mechanism: How One Glitch Causes All Four Symptoms
The ST7789 controller communicates over high-speed serial SPI. It relies on strict byte alignment and the D/C (Data / Command) line:

Scrambled Characters / Corrupted Graphics: Text and graphics are sent as streams of 16-bit RGB565 color pixels. If the display misses even a single clock pulse on SCL, every subsequent byte is shifted by 1 bit. A 1-bit shift completely scrambles the pixel data, turning sharp font glyphs into chaotic, scrambled noise.
Off-Centered Text: To draw text or menus, the driver first sends coordinate window commands (0x2A CASET for columns, 0x2B RASET for rows). If electrical noise corrupts these coordinates, the drawing box is mapped to the wrong part of the display memory, causing elements to render shifted or wrapped around the screen.
White Lines: In ST7789 IPS panels, uninitialized or unwritten display memory (or memory with inverted color polarity) defaults to bright white. If a corrupted coordinate window cuts off rendering early, the remainder of the scanlines display as stark white lines.
Screen "Randomly" Not Rendering: If noise glitches the D/C pin or byte stream, the ST7789 can interpret incoming pixel data as controller commands. Specific bytes match ST7789 control registers like 0x28 (Display OFF) or 0x10 (Enter Sleep Mode), causing the screen to go completely dark until the next reboot.
2. The Primary Causes (Ranked by Probability)
Cause A: Jumper Wires & High SPI Clock Speed (16 MHz)
What’s happening: In display_manager.c, the display SPI clock is set to 16 MHz (LCD_PIXEL_CLOCK_HZ).
While 16 MHz works cleanly on a fabricated PCB with short ground-plane traces, standard DuPont jumper wires (10–20 cm) and breadboards have significant parasitic capacitance and inductance.
At 16 MHz, signal ringing, edge degradation, and crosstalk between adjacent wires (especially between SCL GPIO 18 and SDA GPIO 23) frequently cause missed or phantom clock edges.
Cause B: 3.3V Power Rail Droop / Ground Bounce (Wi-Fi Surges)
What’s happening: The ESP32's Wi-Fi radio draws rapid current pulses of 250 mA – 350 mA when transmitting beacons or scanning. At the same time, the 2.0" LCD backlight draws another 60 mA – 100 mA.
If the display is powered from the ESP32 board's onboard 3.3V regulator through thin breadboard power rails, or if the USB power supply is weak, the 3.3V rail will momentarily dip below ~2.7V.
The ST7789's internal logic browns out and resets to factory defaults (Display OFF, sleep mode enabled, orientation registers reset). Because the ESP32 does not know the screen reset, it keeps blasting pixel data to an unconfigured controller.
A weak or loose GND wire will also cause "ground bounce", shifting the logic threshold and corrupting SPI bits.
Cause C: Loose or Flaky Control Pins (D/C, RST, CS)
RST (GPIO 4): ST7789 reset is active-low. If the reset wire has a loose breadboard contact or is picking up noise, stray voltage drops will trigger random micro-resets mid-frame.
D/C (GPIO 19): If the Data/Command wire has intermittent contact, commands are treated as pixels and pixel data is treated as commands.
CS (GPIO 21): If Chip Select floats or bounces, the ST7789 loses its SPI frame boundary.
Cause D: SPI Clock Mode (Mode 0 vs Mode 3)
The display is configured for SPI Mode 0 (CPOL=0, CPHA=0).
Many clone ST7789 breakout boards incorporate on-board level-shifter resistors or diodes on the SCL/SDA lines that slow down rising edges. In Mode 0, data is latched on the rising edge; if the rise time is sluggish, data is sampled before the line reaches logic HIGH.
3. Physical Checks & Diagnostic Steps (No Code Changes)
Check Jumper Wire Quality & Length:
Keep the wires between the ESP32 and ST7789 as short as possible (ideally under 10 cm / 4 inches).
Ensure SCL (GPIO 18) and SDA (GPIO 23) are not twisted tightly together with power lines or buzzer/motor wires.
Add a Decoupling Capacitor:
Place a 10 µF to 100 µF electrolytic capacitor (or a 0.1 µF ceramic capacitor) directly across the display module's VCC and GND pins. This absorbs the voltage dips caused by Wi-Fi spikes.
Verify Common Ground:
Ensure the display GND has a solid, direct connection to the ESP32 GND pin (not chained through multiple breadboard tie-points).
Inspect the RST and BLK Pins:
If your display module has a BLK (backlight) pin, ensure it is firmly connected to 3.3V rather than left floating.
Make sure the RST wire on GPIO 4 is firmly seated.

Display has already been changed to 8 mhz. lower frame rate does not matter

1. The Underlying Mechanism: How One Glitch Causes All Four Symptoms The ST7789 controller communicates over high-speed serial SPI. It relies on strict byte alignment and the D/C (Data / Command) line: Scrambled Characters / Corrupted Graphics: Text and graphics are sent as streams of 16-bit RGB565 color pixels. If the display misses even a single clock pulse on SCL, every subsequent byte is shifted by 1 bit. A 1-bit shift completely scrambles the pixel data, turning sharp font glyphs into chaotic, scrambled noise. Off-Centered Text: To draw text or menus, the driver first sends coordinate window commands (0x2A CASET for columns, 0x2B RASET for rows). If electrical noise corrupts these coordinates, the drawing box is mapped to the wrong part of the display memory, causing elements to render shifted or wrapped around the screen. White Lines: In ST7789 IPS panels, uninitialized or unwritten display memory (or memory with inverted color polarity) defaults to bright white. If a corrupted coordinate window cuts off rendering early, the remainder of the scanlines display as stark white lines. Screen "Randomly" Not Rendering: If noise glitches the D/C pin or byte stream, the ST7789 can interpret incoming pixel data as controller commands. Specific bytes match ST7789 control registers like 0x28 (Display OFF) or 0x10 (Enter Sleep Mode), causing the screen to go completely dark until the next reboot. 2. The Primary Causes (Ranked by Probability) Cause A: Jumper Wires & High SPI Clock Speed (16 MHz) What’s happening: In display_manager.c, the display SPI clock is set to 16 MHz (LCD_PIXEL_CLOCK_HZ). While 16 MHz works cleanly on a fabricated PCB with short ground-plane traces, standard DuPont jumper wires (10–20 cm) and breadboards have significant parasitic capacitance and inductance. At 16 MHz, signal ringing, edge degradation, and crosstalk between adjacent wires (especially between SCL GPIO 18 and SDA GPIO 23) frequently cause missed or phantom clock edges. Cause B: 3.3V Power Rail Droop / Ground Bounce (Wi-Fi Surges) What’s happening: The ESP32's Wi-Fi radio draws rapid current pulses of 250 mA – 350 mA when transmitting beacons or scanning. At the same time, the 2.0" LCD backlight draws another 60 mA – 100 mA. If the display is powered from the ESP32 board's onboard 3.3V regulator through thin breadboard power rails, or if the USB power supply is weak, the 3.3V rail will momentarily dip below ~2.7V. The ST7789's internal logic browns out and resets to factory defaults (Display OFF, sleep mode enabled, orientation registers reset). Because the ESP32 does not know the screen reset, it keeps blasting pixel data to an unconfigured controller. A weak or loose GND wire will also cause "ground bounce", shifting the logic threshold and corrupting SPI bits. Cause C: Loose or Flaky Control Pins (D/C, RST, CS) RST (GPIO 4): ST7789 reset is active-low. If the reset wire has a loose breadboard contact or is picking up noise, stray voltage drops will trigger random micro-resets mid-frame. D/C (GPIO 19): If the Data/Command wire has intermittent contact, commands are treated as pixels and pixel data is treated as commands. CS (GPIO 21): If Chip Select floats or bounces, the ST7789 loses its SPI frame boundary. Cause D: SPI Clock Mode (Mode 0 vs Mode 3) The display is configured for SPI Mode 0 (CPOL=0, CPHA=0). Many clone ST7789 breakout boards incorporate on-board level-shifter resistors or diodes on the SCL/SDA lines that slow down rising edges. In Mode 0, data is latched on the rising edge; if the rise time is sluggish, data is sampled before the line reaches logic HIGH. 3. Physical Checks & Diagnostic Steps (No Code Changes) Check Jumper Wire Quality & Length: Keep the wires between the ESP32 and ST7789 as short as possible (ideally under 10 cm / 4 inches). Ensure SCL (GPIO 18) and SDA (GPIO 23) are not twisted tightly together with power lines or buzzer/motor wires. Add a Decoupling Capacitor: Place a 10 µF to 100 µF electrolytic capacitor (or a 0.1 µF ceramic capacitor) directly across the display module's VCC and GND pins. This absorbs the voltage dips caused by Wi-Fi spikes. Verify Common Ground: Ensure the display GND has a solid, direct connection to the ESP32 GND pin (not chained through multiple breadboard tie-points). Inspect the RST and BLK Pins: If your display module has a BLK (backlight) pin, ensure it is firmly connected to 3.3V rather than left floating. Make sure the RST wire on GPIO 4 is firmly seated. Display has already been changed to 8 mhz. lower frame rate does not matter

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Reference: rasmus/MTGcompanion#1